Halo-Implanted Partially Depleted Silicon-on-Insulator MOSFET with Optimized Buried Oxide Substrate for Short Channel Effects Mitigation

International Journal of Electronics and Communication Engineering

© 2025 by SSRG - IJECE Journal

Volume 12 Issue 8

Year of Publication : 2025

Authors : Shaweta Khullar, Harish Chandra Mohanta

10.14445/23488549/IJECE-V12I8P121

How to Cite?

Shaweta Khullar, Harish Chandra Mohanta, "Halo-Implanted Partially Depleted Silicon-on-Insulator MOSFET with Optimized Buried Oxide Substrate for Short Channel Effects Mitigation," SSRG International Journal of Electronics and Communication Engineering, vol. 12,  no. 8, pp. 234-243, 2025. Crossref, https://doi.org/10.14445/23488549/IJECE-V12I8P121

Abstract:

In traditional bulk MOSFETs, the MOSFET dimensions shrink below the 90 nm barrier, and Short-Channel Effects (SCE) emerge, which weaken gate control. These include threshold voltage roll-off, increased leakage currents, and Drain-Induced Barrier Lowering (DIBL). While offering better electrostatic control, Fully Depleted Silicon-on-Insulator MOSFETs (FD-SOI) and Partially Depleted Silicon-on-Insulator (PD-SOI) MOSFETs still have inherent drawbacks in ultra-scaled nodes. Since FD-SOI MOSFET needs silicon thickness to be controlled precisely, along with exact doping, it is harder and more expensive to manufacture. Although it reduces some SCEs and increases gate-to-body coupling, it has some leakage current and electrostatic limitations. To overcome these limitations, a proposed PD-SOI MOSFET design uses source-side halo implantation with a tunnel diode within the Buried Oxide (BOX) layer. Halo implantation reduces channel electrostatics by the depletion region effects originating from both sides of the source and drain implants, while an integrated tunnel diode provides another current path to balance leakage currents and improve electrostatic control. The proposed device combines these two approaches to suppress SCE and further improve the performance of the device, with the potential for higher SCE suppression as well as higher performance of the devices in next-generation MOSFETs. The simulated results achieve the low threshold voltage and low DIBL, reducing the SCE in the proposed device.

Keywords:

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), Short-Channel Effects (SCE), Fully Depleted Silicon-On-Insulator (FD-SOI) MOSFET, Partially Depleted Silicon-On-Insulator (PD-SOI) MOSFET, Buried Oxide (BOX) layer.

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