Design of Stable 10T FinFET SRAM Cell for Operation in Sub-Threshold Regime

International Journal of Electrical and Electronics Engineering

© 2025 by SSRG - IJEEE Journal

Volume 12 Issue 6

Year of Publication : 2025

Authors : Ajjay S. Gaadhe, Yuvraj V. Parkale

10.14445/23488379/IJEEE-V12I6P118

How to Cite?

Ajjay S. Gaadhe, Yuvraj V. Parkale, "Design of Stable 10T FinFET SRAM Cell for Operation in Sub-Threshold Regime," SSRG International Journal of Electrical and Electronics Engineering, vol. 12,  no. 6, pp. 206-213, 2025. Crossref, https://doi.org/10.14445/23488379/IJEEE-V12I6P118

Abstract:

The growing prevalence of portable electronic devices has led to an increased reliance on static random-access memory (SRAM) as a critical element in contemporary VLSI circuit design. To meet the rising demand for energy-efficient operation, sub-threshold SRAM design has gained attention for its ability to reduce power consumption. However, this approach presents challenges in maintaining adequate stability. This work investigates the development and evaluation of a 10-transistor (10T) FinFET SRAM bit cell to enhance stability. The paper provides complete design parameters along with an analysis of fin dimensions because they control the electrical performance in 10T SRAM cells. When properly set, fin width and height configurations allow drive strength and leakage balance, leading to increased noise margin performance. The proposed fin configuration and a separate read and write path establish an effective breakdown between read and write operations. The separation between read and write operations and control of drive strength of transistors enhances the stability of the entire system by preventing read disturbances when writing occurs, as well as write disturbances during reading. All simulations were executed through the Microwind 3.9 environment operated with 14 nm FinFET process technology. The results indicate that the 10T SRAM cell demonstrates significantly enhanced stability compared to the conventional CMOS and 6-transistor (6T) FinFET design. In particular, the 10T cell exhibits improvements of 65% in Read Static Noise Margin (RSNM) compared to conventional CMOS technology, maintaining the Write Static Noise Margin (WSNM) with incremental improvement. Besides, 10T FinFET cell demonstrates 4% improvement in RSNM and WSNM compared t 6T FinFET at the 14 nm technology node. These findings suggest that careful device sizing and architectural modifications can enhance SRAM reliability in advanced technology nodes.

Keywords:

VLSI, Microelectronics, FinFET, Write ability, Read stability, Static noise margin, Power.

References:

[1] Benton H. Calhoun, and Anantha P. Chandrakasan, “Static Noise Margin Variation for Sub‐Threshold SRAM in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, no. 7, pp. 1673-1679, 2006.
[CrossRef] [Google Scholar] [Publisher Link]
[2] Seng Oon Toh et al., “Characterization of Dynamic SRAM Stability in 45nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 46, no. 11, pp. 2702-2712, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Benton H.Calhoun, Alice Wang, and Anantha Chandrakasan, “Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits,” IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, 2005.
[CrossRef] [Google Scholar] [Publisher Link]
[4] Akshay Bhaskar, “Design and Analysis of Low Power SRAM Cells,” 2017 Innovations in Power and Advanced Computing Technologies (i-PACT), Vellore, India, pp. 1-5, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[5] Yu Cao et al., “The Predictive Technology Model in the Late Silicon Era and Beyond,” Foundations and Trends in Electronic Design Automation, vol. 3, no. 4, pp. 305-401, 2008.
[CrossRef] [Google Scholar] [Publisher Link]
[6] Mo Maggie Zhang, “Performance Comparison of SRAM Cells Implemented in 6, 7 and 8-Transistor Cell Topologies”, Electrical and Computer Engineering, University of California, Davis, 2008.
[Google Scholar] [Publisher Link]
[7] P. Upadhyay et al., “Read Stability and Power Analysis of a Proposed Novel 8 Transistor Static Random Access Memory Cell in 45 nm Technology,” Scientia Iranica: Transaction D, vol. 21, no. 3, pp. 953-962, 2014.
[Google Scholar] [Publisher Link]
[8] Rohit Lorenzo, and Saurabh Chaudhury A Novel 9T SRAM Architecture for Low Leakage and High Performance,” Analog Integrated Circuits and Signal Processing, vol. 92, no. 2, pp. 315-325, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Soumitra Pal et al., “Half-Select-Free Low-Power Dynamic Loop Cutting Write Assist SRAM Cell for Space Applications,” IEEE Transactions on Electronic Devices, vol. 67, no. 1, pp. 80-89, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Debajit Bhattacharya, and Niraj K. Jha, “FinFETs: From Devices to Architectures,” Advances in Electronics, vol. 2014, no. 1, pp. 1-12, 2014.
[CrossRef] [Google Scholar] [Publisher Link]
[11] Appikatla Phani Kumar, and Rohit Lorenzo, “Performance Analysis of DMG-GOS Junctionless FinFET with High-K Spacer,” 2022 IEEE Silchar Subsection Conference (SILCON), Silchar, India, pp. 1-5, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Mahmood Uddin Mohammed et al., “FinFET-Based SRAMs in Sub-10nm Domain,” Microelectronics Journal, vol. 114, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[13] Gabriel Torrens et al., “A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors,” IEEE Transactions on Emerging Topics in Computing, vol. 7, no. 3, pp. 447-455, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[14] Manpreet Kaur, and Ravi Kumar Sharma, “Comparative Parametric Analysis, For Stability of 6T and 8T SRAM Cell,” International Journal of Advances in Engineering & Technology, vol. 5, no. 1, pp. 503-514, 2012.
[Google Scholar] [Publisher Link]
[15] Shilpi Birla, R.K. Singh, and Manisha Pattnaik, “Static Noise Margin Analysis of Various SRAM Topologies,” IACSIT International Journal of Engineering and Technology, vol. 3, no. 3, pp. 304-306, 2011.
[CrossRef] [Google Scholar] [Publisher Link]
[16] Sayeed Ahmad, Naushad Alam, and Mohd. Hasan, “A Robust 10T SRAM Cell with Enhanced Read Operation,” International Journal of Computer Applications, vol. 129, no. 2, pp. 7-12, 2015.
[CrossRef] [Google Scholar] [Publisher Link]
[17] Aswathy A. Kumar, and Anu Chalil, “Performance Analysis of 6T SRAM Cell on Planar and FinFET Technology,” 2019 International Conference on Communication and Signal Processing, Chennai, India, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[18] Evert Seevinck et al., “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 748-754, 1987.
[CrossRef] [Google Scholar] [Publisher Link]
[19] Surbhi Bharti et al., “Performance Analysis of SRAM Cell Designed using MOS and Floating-Gate MOS for Ultralow Power Technology,” 2019 4th International Conference on Internet of Things: Smart Innovation and Usages (IoT-SIU), Ghaziabad, India, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[20] Rohit Lorenzo, and Saurabh Chaudhury, “A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability,” Wireless Personal Communications, vol. 94, no. 4, pp. 3513-3529, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[21] Himanshu Banga, and Dheeraj Agarwal, “Single bit-line 10T SRAM cell for low power and high SNM,” 2017 International Conference on Recent Innovations in Signal Processing and Embedded Systems (RISE), Bhopal, India, pp. 433- 438, 2017. [CrossRef] [Google Scholar] [Publisher Link]
[22] Evert Seevinck et al., “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 748-754, 1987.
[CrossRef] [Google Scholar] [Publisher Link]
[23] Chandrabhan Kushwah, and Santosh K. Vishvakarma, “Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin,” Progress in VLSI Design and Test, Springer, Berlin, Heidelberg, vol. 7373, pp. 139-146, 2012.
[CrossRef] [Google Scholar] [Publisher Link]
[24] Koichi Takeda et al., “Redefinition of Write Margin for Next‐Generation SRAM and Write‐Margin Monitoring Circuit,” 2006 IEEE International Solid State Circuits Conference‐Digest of Technical Papers, San Francisco, CA, USA, pp. 2602-2611, 2006.
[CrossRef] [Google Scholar] [Publisher Link]
[25] Nicolas Gierczynski et al., A New Combined Methodology for Write‐Margin Extraction of Advanced SRAM,” 2007 IEEE International Conference on Microelectronic Test Structures, Bunkyo-ku, Japan, pp. 97-100, 2007.
[CrossRef] [Google Scholar] [Publisher Link]
[26] Jiajing Wang et al., Analyzing Static and Dynamic Write Margin for Nanometer SRAMs,” Proceedings of the 2008 international symposium on Low Power Electronics & Design, Bangalore India, pp. 129-134, 2008.
[CrossRef] [Google Scholar] [Publisher Link]
[27] Kevin Zhang et al.: A 3‐GHz70‐mb SRAM in 65‐nm CMOS Technology with Integrated Column‐Based Dynamic Power Supply,” IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 146-151, 2005.
[CrossRef] [Google Scholar] [Publisher Link]
[28] Ruchi, and Sudeb Dasgupta, “Compact Analytical Model to Extract Write Static Noise Margin (wsnm)for SRAM Cell at 45‐nm and 65‐nm Nodes,” IEEE Transactions on Semiconductor Manufacturing, vol. 31, no. 1, pp. 136-143, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[29] Evert Seevinck, Frans J. List, and Jan Lohstroh, “Static‐Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 748-754, 1987.
[CrossRef] [Google Scholar] [Publisher Link]