ICETSST-2018 - Part 1
Title/Author Name |
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|---|---|
| Design and Implementation of Full Adders using QCA - V.Subashini , R.S. Koteeshwari |
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| Design and Application of Approximate Circuit by SAIF Pruning - K.Mahalakshmi S.Chitra M.E |
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| Probability-Driven Timing Error Based Multibit Flip-Flop with Clock Gating - B.Rajeshwari M.AntonyJegan M.E |
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| VLSI Implementation of Dead Pixel Removal using Three Cell Sorting Median Filter - Murugan.G , Mrs.K.Theivajeyaselvi ME |